Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment

Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young
{"title":"Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment","authors":"Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young","doi":"10.1145/3394885.3431565","DOIUrl":null,"url":null,"abstract":"In multi-FPGA systems, time-division multiplexing (TDM) is a widely used technique to transfer signals between FPGAs. While TDM can greatly increase logic utilization, the inter-FPGA delay will also become longer. A good time-multiplexing scheme for inter-FPGA signals is very important for optimizing the system performance. In this work, we propose a fast algorithm to generate high quality time-multiplexed routing results for multiple FPGA systems. A hybrid routing algorithm is proposed to route the nets between FPGAs, by maze routing and by a fast minimum terminal spanning tree method. After obtaining a routing topology, a two-step method is applied to perform TDM assignment to optimize timing, which includes an initial assignment and a competitive-based refinement. Experiments show that our system-level routing and TDM assignment algorithm can outperform both the top winner of the ICCAD 2019 Contest and the state-of-the-art methods. Moreover, compared to the state-of-the-art works [17], [22], our approach has better run time by more than 2X with better or comparable TDM performance.","PeriodicalId":186307,"journal":{"name":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3394885.3431565","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

In multi-FPGA systems, time-division multiplexing (TDM) is a widely used technique to transfer signals between FPGAs. While TDM can greatly increase logic utilization, the inter-FPGA delay will also become longer. A good time-multiplexing scheme for inter-FPGA signals is very important for optimizing the system performance. In this work, we propose a fast algorithm to generate high quality time-multiplexed routing results for multiple FPGA systems. A hybrid routing algorithm is proposed to route the nets between FPGAs, by maze routing and by a fast minimum terminal spanning tree method. After obtaining a routing topology, a two-step method is applied to perform TDM assignment to optimize timing, which includes an initial assignment and a competitive-based refinement. Experiments show that our system-level routing and TDM assignment algorithm can outperform both the top winner of the ICCAD 2019 Contest and the state-of-the-art methods. Moreover, compared to the state-of-the-art works [17], [22], our approach has better run time by more than 2X with better or comparable TDM performance.
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多fpga协同优化:混合路由和基于竞争的时分复用分配
在多fpga系统中,时分复用(TDM)是一种在fpga之间广泛使用的信号传输技术。虽然时分复用可以大大提高逻辑利用率,但fpga间的延迟也会变长。一个好的fpga间信号时复用方案对于优化系统性能是非常重要的。在这项工作中,我们提出了一种快速算法,可以为多个FPGA系统生成高质量的时间复用路由结果。提出了一种混合路由算法,通过迷宫路由和快速最小终端生成树方法在fpga之间路由网络。在获得路由拓扑结构后,采用初始分配和基于竞争的细化两步方法对TDM进行时序优化。实验表明,我们的系统级路由和TDM分配算法可以优于ICCAD 2019竞赛的最高获胜者和最先进的方法。此外,与最先进的工作[17],[22]相比,我们的方法运行时间缩短了2倍以上,TDM性能更好或相当。
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