Designing optimum carry-skip adders

Abstract

A method for designing optimum-speed one-level carry-skip adders is described. This method always yields the fastest adders if the assumptions of A. Guyot et al. (1987) hold, that is if the ripple time (a circuit parameter) of a carry signal is a linear function of the number of bit positions that the carry signal propagates through, and if the skip time (another circuit parameter) of a carry signal is a linear function of the number of blocks of bit positions skipped by the signal, or if these two parameters are such mildly nonlinear functions that can be modeled by a linear function without any effect on any of the results obtained. The circuit design method is useful because in device technologies such as 2-AlU CMOS the nonlinearities are often insignificant. The present results are compared with those of Guyot et al. as well as with the results of V.G. Oklobdzija and E.R. Barnes (1985).<>