Miller plateau as an indicator of SiC MOSFET gate oxide degradation

Abstract

This paper presents a new indicator of SiC MOSFET gate oxide degradation based on Miller plateau. The physical mechanism of Miller plateau shift with gate oxide electric field is first analyzed. The relationship between Miller plateau and ambient temperature is then explored by theoretical analysis. The electro-thermal simulation is conducted in LTSpice to verify the Miller plateau shift with ambient temperature. Besides, 20 groups of High Electric Field (HEF) acceleration tests are conducted with Vgs stress amplitude of 25 V, 30V, 35V, 40V and stress duration of 10, 40, 70, 85, 100 hours. 5 SCT2120AF SiC MOSEFTs from Rohm are stressed in each group. After ageing tests, the stressed devices are used to verify dynamic characteristic change in the designed double pulse test platform. After 100-hour HEF tests with 40V Vgs stress, Miller plateau shift can reach up to 1.5V. Finally, comparison is made among Miller plateau, threshold voltage and gate resistor turn-on energy. Analysis shows that Miller plateau can be used as an indicator of SiC MOSFET gate oxide degradation with detectable amplitude shift as well as inherent gate driver integration and online monitoring characteristics.