A time-predictable dual-core prototype on FPGA

ACM SE '10 Pub Date : 2010-04-15 DOI:10.1145/1900008.1900020
Satya Mohan Raju Gudidevuni, Wei Zhang
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Abstract

This paper describes the design and implementation of time-predictable dual-core architecture on Xilinx FPGA. The emphasis is to observe the impact of various cache replacement algorithms on the time-predictability of a high priority thread, in a multi-core architecture. This design is done in verilog and consists of two cores, each with a simple 5-stage in-order pipeline and a private L1-cache. This is further connected to a shared L2 cache and a RAM. The design is synthesized in Xilinx ISE and its performance will be tested on Virtex-6 FPGA.
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基于FPGA的时间可预测双核原型
本文介绍了在Xilinx FPGA上设计和实现可预测时间的双核架构。重点是观察在多核架构中,各种缓存替换算法对高优先级线程的时间可预测性的影响。该设计是在verilog中完成的,由两个核心组成,每个核心都有一个简单的5级顺序管道和一个私有l1缓存。这进一步连接到一个共享的二级缓存和一个RAM。该设计是在Xilinx ISE中合成的,其性能将在Virtex-6 FPGA上进行测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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