{"title":"ESL - The Next Leadership Opportunity for India?","authors":"A. Naumann","doi":"10.1109/ICVD.2005.92","DOIUrl":null,"url":null,"abstract":"Summary form only given. This paper lectures on the increasingly critical role played by electronic system level (ESL) design tools in the development of the complex system-on-chip (SoC) devices that are now the indispensable engines of advanced consumer and communications products. Drawing upon his experience in managing CoWare, which has world-class software development resources in India, the author argues that ESL tool development expertise can be an effective differentiator for Indian software engineering. This paper discusses the growing impact of SoC technology on the global electronics market, and the factors driving it. In particular, contrary to the conventional wisdom, the design cost per gate continues to fall - because rising mask costs are more than offset by the massive increase in the number of gates per chip. This increase in gate capacity presents SoC designers not only with a significant market opportunity, but also with a serious design challenge - how to integrate so much functionality into one chip without the multiple re-spins that destroy a product's time to market and bury its design budget. Also discussed is the ESL design methodology, and it is argued that the adoption of such a methodology is a pre-requisite for meeting this SoC design challenge. This paper argues that Indian engineers - with their proven expertise in software modelling and development - can occupy a pole position in this new industrial revolution.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI design (Print)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.2005.92","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Summary form only given. This paper lectures on the increasingly critical role played by electronic system level (ESL) design tools in the development of the complex system-on-chip (SoC) devices that are now the indispensable engines of advanced consumer and communications products. Drawing upon his experience in managing CoWare, which has world-class software development resources in India, the author argues that ESL tool development expertise can be an effective differentiator for Indian software engineering. This paper discusses the growing impact of SoC technology on the global electronics market, and the factors driving it. In particular, contrary to the conventional wisdom, the design cost per gate continues to fall - because rising mask costs are more than offset by the massive increase in the number of gates per chip. This increase in gate capacity presents SoC designers not only with a significant market opportunity, but also with a serious design challenge - how to integrate so much functionality into one chip without the multiple re-spins that destroy a product's time to market and bury its design budget. Also discussed is the ESL design methodology, and it is argued that the adoption of such a methodology is a pre-requisite for meeting this SoC design challenge. This paper argues that Indian engineers - with their proven expertise in software modelling and development - can occupy a pole position in this new industrial revolution.