{"title":"Keynote Talk: A History of the VLSI Design Conference","authors":"V. Agrawal","doi":"10.1109/VLSID.2012.23","DOIUrl":"https://doi.org/10.1109/VLSID.2012.23","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134330795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Keynote Talk: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines","authors":"Rajesh K. Gupta","doi":"10.1109/VLSID.2012.26","DOIUrl":"https://doi.org/10.1109/VLSID.2012.26","url":null,"abstract":"","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122814881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Pattanam, P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, V. Gautham, Raju Bala Showry Pudota
Summary form only given. System on Chip (SoC) design promises to revolutionize a vast array of products and markets. Access to advanced semiconductor technology is opening up new markets and facilitating innovation at a rate which we have not seen before. All of this bodes well for a vibrant semiconductor industry its associated EDA industry. Yet, there is a problem. The cost of design for SoC devices is growing at a rapid pace. Complexity is contributing to this cost rise. Because of shrinking market windows, it also becomes necessary to reuse semiconductor IP, either from third party sources or prior internal designs there is just not enough time to design much of these chips from scratch. But the quality and completeness of this IP is often not completely known, further contributing to the cost and schedule uncertainty of SoC devices. Structured design methodologies that focus on early identification and correction of design issues, rigorous methods to qualify semiconductor IP and automated approaches to assembling the components of an SoC promise to address many of the cost and schedule challenges. This early analysis methodology has been called "SoC Realization". In this panel discussion, we will explore the meaning of SoC Realization and discuss its impact on the cost and schedule for advanced SoC designs.
{"title":"Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere?","authors":"S. Pattanam, P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, V. Gautham, Raju Bala Showry Pudota","doi":"10.1109/VLSID.2012.42","DOIUrl":"https://doi.org/10.1109/VLSID.2012.42","url":null,"abstract":"Summary form only given. System on Chip (SoC) design promises to revolutionize a vast array of products and markets. Access to advanced semiconductor technology is opening up new markets and facilitating innovation at a rate which we have not seen before. All of this bodes well for a vibrant semiconductor industry its associated EDA industry. Yet, there is a problem. The cost of design for SoC devices is growing at a rapid pace. Complexity is contributing to this cost rise. Because of shrinking market windows, it also becomes necessary to reuse semiconductor IP, either from third party sources or prior internal designs there is just not enough time to design much of these chips from scratch. But the quality and completeness of this IP is often not completely known, further contributing to the cost and schedule uncertainty of SoC devices. Structured design methodologies that focus on early identification and correction of design issues, rigorous methods to qualify semiconductor IP and automated approaches to assembling the components of an SoC promise to address many of the cost and schedule challenges. This early analysis methodology has been called \"SoC Realization\". In this panel discussion, we will explore the meaning of SoC Realization and discuss its impact on the cost and schedule for advanced SoC designs.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128898509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The ongoing trend towards nanoscale technologies creates enormous opportunities for realizing the connected consumer vision. In this talk, the authors illustrate how NXP Semiconductors Nexperia's computing architecture addresses the connected consumer requirements of low power, vibrant media capabilities, multi-standard communication pipes, and consumer price points. The authors also illustrate how the architecture helps to overcome the design challenges of TTM and complex integration of functions and features
{"title":"Nexperia Computing Architecture for Connected Consumer Applications","authors":"J. A. D. Oliveira","doi":"10.1109/VLSID.2007.115","DOIUrl":"https://doi.org/10.1109/VLSID.2007.115","url":null,"abstract":"The ongoing trend towards nanoscale technologies creates enormous opportunities for realizing the connected consumer vision. In this talk, the authors illustrate how NXP Semiconductors Nexperia's computing architecture addresses the connected consumer requirements of low power, vibrant media capabilities, multi-standard communication pipes, and consumer price points. The authors also illustrate how the architecture helps to overcome the design challenges of TTM and complex integration of functions and features","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126870369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The on-going trend towards nanoscale technologies creates enormous opportunities for integration of complex functions and features. Many challenges have to be overcome in order to exploit nanoscale technologies for mass production: particularly relevant are CMOS SoC challenges such as low power, design for manufacturability and analog design. However, in order to provide a usable electronic function, any SoC needs to be packaged or assembled in a system in package, with its own set of challenges and requirements. The authors illustrate how NXP Semiconductors is overcoming the above
{"title":"Systems, Nano-technology and SiP","authors":"R. P. D. Vries","doi":"10.1109/VLSID.2007.152","DOIUrl":"https://doi.org/10.1109/VLSID.2007.152","url":null,"abstract":"The on-going trend towards nanoscale technologies creates enormous opportunities for integration of complex functions and features. Many challenges have to be overcome in order to exploit nanoscale technologies for mass production: particularly relevant are CMOS SoC challenges such as low power, design for manufacturability and analog design. However, in order to provide a usable electronic function, any SoC needs to be packaged or assembled in a system in package, with its own set of challenges and requirements. The authors illustrate how NXP Semiconductors is overcoming the above","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122757123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The advent of very deep sub-micron technologies coupled with the introduction of newer materials and technologies like copper interconnects, silicon-on-insulator and increased wafer sizes has helped designers to make vital breakthroughs in achieving new technology successes. Bringing smart, creative and yet small devices that satiates human needs in providing connectivity, delivering relevant information and enabling creative expressions is the key for excellence in innovations. The evolution of embedded systems as the key to our world of communication is a significant achievement in the field of information science and technology. Enabling the mobiles with multimedia technology has made them much more powerful & irresistible.
{"title":"Small, Smart, Intelligent and Interactive Handheld Devices","authors":"D. Orton","doi":"10.1109/VLSID.2006.147","DOIUrl":"https://doi.org/10.1109/VLSID.2006.147","url":null,"abstract":"The advent of very deep sub-micron technologies coupled with the introduction of newer materials and technologies like copper interconnects, silicon-on-insulator and increased wafer sizes has helped designers to make vital breakthroughs in achieving new technology successes. Bringing smart, creative and yet small devices that satiates human needs in providing connectivity, delivering relevant information and enabling creative expressions is the key for excellence in innovations. The evolution of embedded systems as the key to our world of communication is a significant achievement in the field of information science and technology. Enabling the mobiles with multimedia technology has made them much more powerful & irresistible.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122199271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only for tutorial. Embedded systems design is a hot application field which merges logic design and processor-based hardware development in a single or few chips solution. Various technologies have been used in the development of embedded systems; microcontroller, DSP processor, ASIC, and now FPGA. Field programmable gate arrays (FPGA) from Xilinx started as glue logic usage stitching functions together. With the introduction of Virtex-II Pro, Xilinx entered embedded processing area. In this tutorial, we show how Xilinx FPGAs can be used in embedded applications. The strengths of Xilinx FPGAs and the supporting development tools are described. A demonstration is provided to show the ease of design and development of a complete system using Xilinx embedded development kit (EDK) software.
{"title":"Embedded Systems Design Using FPGA","authors":"P. Patel","doi":"10.1109/VLSID.2006.83","DOIUrl":"https://doi.org/10.1109/VLSID.2006.83","url":null,"abstract":"Summary form only for tutorial. Embedded systems design is a hot application field which merges logic design and processor-based hardware development in a single or few chips solution. Various technologies have been used in the development of embedded systems; microcontroller, DSP processor, ASIC, and now FPGA. Field programmable gate arrays (FPGA) from Xilinx started as glue logic usage stitching functions together. With the introduction of Virtex-II Pro, Xilinx entered embedded processing area. In this tutorial, we show how Xilinx FPGAs can be used in embedded applications. The strengths of Xilinx FPGAs and the supporting development tools are described. A demonstration is provided to show the ease of design and development of a complete system using Xilinx embedded development kit (EDK) software.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134293807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only for tutorial. In this section, the principles of operation of data-converters, the different architectures, and the important specification parameters are presented. We begin by discussing the fundamental processes of analog-digital conversion: quantization, sampling, resolution. The various figures-of-merit of an ADC such as integral nonlinearity (INL), differential nonlinearity (DNL) and signal-noise ratio (SNR) are then presented. In the second part of this section, a classification of well-known A/D converter architectures is presented. The advantages and disadvantages of each of these architectures, their respective resolution-speed-power consumption ranges, and the applications in which they find use are discussed.
{"title":"System Aspects of Analog to Digital Converter Designs","authors":"S. Pavan, P. Easwaran, C. Srinivasan","doi":"10.1109/VLSID.2006.154","DOIUrl":"https://doi.org/10.1109/VLSID.2006.154","url":null,"abstract":"Summary form only for tutorial. In this section, the principles of operation of data-converters, the different architectures, and the important specification parameters are presented. We begin by discussing the fundamental processes of analog-digital conversion: quantization, sampling, resolution. The various figures-of-merit of an ADC such as integral nonlinearity (INL), differential nonlinearity (DNL) and signal-noise ratio (SNR) are then presented. In the second part of this section, a classification of well-known A/D converter architectures is presented. The advantages and disadvantages of each of these architectures, their respective resolution-speed-power consumption ranges, and the applications in which they find use are discussed.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114021266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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