A cellular NoC architecture based on butterfly network coding (CBNoC)

Abstract

The intra-chip communication latency and power consumption become the main bottleneck of the development of multi-core processors. Network-on-Chip (NoC) paradigm is proposed to meet these stringent requirements. Since the wireless network interconnection can achieve high speed data transmission with low power consumption, this paper proposes a cellular NoC architecture based on multiple butterfly network coding clusters with low latency. Data packets and control packets are transmitted on the wireless channel and the wired channel, separately. We also design a Z-X-Y path routing algorithm to achieve the shortest routing. Experiment results prove that, compared with Mesh, the proposed architecture can achieve at least 8% average latency reduction with slight resource increment.