Constraint-free analog placement with topological symmetry structure

Abstract

In analog circuits, blocks need to be placed symmetrically to satisfy the devices matching. Different from the existing constraint-driven approaches, the proposed topological symmetry structure enables us to generate a symmetrical placement without any constraint. Simulated annealing is utilized as the framework of the optimization, and we propose new move operation to maintain the placement's topological symmetry. By inserting dummy blocks, we present a physical skewed symmetry structure allowing non-symmetry partly, so that to enhance the placement on area and wire length. Besides, we incorporate regularity into the evaluation of placement. Experiments shows that our approach generated topological complete symmetry placements without much compromise on chip area and wire length, compared to the placements with no symmetry.