{"title":"Design of low-ripple multi-topology step-down switched capacitor power converter with adaptive control system","authors":"Vazgen Melikyan, V. Galstyan","doi":"10.1109/EWDTS.2014.7027083","DOIUrl":null,"url":null,"abstract":"The paper presents a multi-topology step-down switched-capacitor (SC) converter with a novel adaptive control. The control system adjusts the number of SC cores to significantly reduce output voltage ripple, as well as performs dynamic frequency control depending on actual load of the converter. By means of new dynamic control system, the converter achieves 50ns response time and 24mV of maximal output ripple over wide range of load currents. Due to multi-topology structure high efficiency is provided over 1.5V range of input voltage. The converter is designed in 40nm CMOS process using the proposed technique.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2014.7027083","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The paper presents a multi-topology step-down switched-capacitor (SC) converter with a novel adaptive control. The control system adjusts the number of SC cores to significantly reduce output voltage ripple, as well as performs dynamic frequency control depending on actual load of the converter. By means of new dynamic control system, the converter achieves 50ns response time and 24mV of maximal output ripple over wide range of load currents. Due to multi-topology structure high efficiency is provided over 1.5V range of input voltage. The converter is designed in 40nm CMOS process using the proposed technique.
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