Jong‐Wook Lee, D. H. Vo, Sang-Hoon Hong, Quoc-Hung Huynh
{"title":"A fully integrated high security NFC target IC using 0.18 μm CMOS process","authors":"Jong‐Wook Lee, D. H. Vo, Sang-Hoon Hong, Quoc-Hung Huynh","doi":"10.1109/ESSCIRC.2011.6044944","DOIUrl":null,"url":null,"abstract":"We present a fully-integrated compact (1.1 mm2) target device for Near Field Communication (NFC). The design of the key analog part of the tag IC is presented, which includes a robust demodulator for 10% ASK envelope detection, a high-quality random number generator, an adaptive RF limiter, and a low power clock generator. A 128 bit advanced encryption standard (AES) with new cyclic key generation is used for secure data encryption and decryption. An on-chip 4Kb EEPROM is used to support the AES operation. The tag chip is fabricated in a 1-poly 6-metal low-power (LP) 0.18 μm CMOS process with a CoSi2-Schottky diode and EEPROM process.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2011.6044944","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
We present a fully-integrated compact (1.1 mm2) target device for Near Field Communication (NFC). The design of the key analog part of the tag IC is presented, which includes a robust demodulator for 10% ASK envelope detection, a high-quality random number generator, an adaptive RF limiter, and a low power clock generator. A 128 bit advanced encryption standard (AES) with new cyclic key generation is used for secure data encryption and decryption. An on-chip 4Kb EEPROM is used to support the AES operation. The tag chip is fabricated in a 1-poly 6-metal low-power (LP) 0.18 μm CMOS process with a CoSi2-Schottky diode and EEPROM process.