Ordered escape routing using network flow and optimization model

Abstract

With the advancement in technology, BGA based integrated circuits for robotics and other devices are being prepared in small sizes with more pin count. This increase in number requires more number of pins to be escaped from the inner side of the IC towards the escape boundary. Ordered escape routing is very important due to its great impact on area and length routing at later stage. Basic design rules of planarity and capacity along with constraints like length matching make the ordered escape routing problem more difficult. In this paper we formulate flow model on the basis of inter-pin capacity. Using flow model we propose optimization model that solves ordered escape routing problem under design constraints. Evaluation of model using randomly generated examples shows that maximum possible nets are being routed by the model.