The Model Checking Problem in Networks with Quasi-Equal Clocks

Christian Herrera, B. Westphal
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引用次数: 2

Abstract

Quasi-equal clocks reduction for networks of timed automata yields significant savings in verification costs of properties of timed automata by replacing clocks in equivalence classes by representative clocks. In this work we present the theoretical analysis that quantifies and justifies those savings. We propose new space and time bounds that characterise a less expensive model checking effort in transformed networks wrt. The effort in original networks with quasi-equal clocks. Additionally, we carry out improvements to our transformation algorithm in order to maximize savings wrt. Space and time, and we eliminate all remaining semantic assumptions on networks introduced to soundly apply the reduction of clocks.
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准等时钟网络中的模型检验问题
时间自动机网络的准相等时钟缩减通过用代表性时钟代替等价类中的时钟,显著节省了时间自动机性质的验证成本。在这项工作中,我们提出了量化和证明这些节省的理论分析。我们提出了新的空间和时间限制,以表征转换网络中更便宜的模型检查工作。在具有准相等时钟的原始网络中的努力。此外,我们对转换算法进行了改进,以最大限度地节省wrt。空间和时间,我们消除了网络上所有剩余的语义假设,以合理地应用时钟的减少。
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