Interconnect impedance optimization for high speed IO up to 12Gbps under HVM condition

Abstract

Differential impedance optimization is critical for high-speed IO design and has attracted lot of interests for decades. This paper focuses on impedance optimization on a general purpose server design for 10Gbps and above and use SAS3 (Serial Attached SCSI Gen3) as example under HVM (high volume manufacturing) condition. The study starts with theoretical analysis on a two-port network of three cascaded transmission lines to prove that there is an optimal characteristic impedance value of the middle section which can bring the lowest reflection and best transmission to the entire two-port network. In the SAS3 impedance optimization study, statistical distribution for each design variable is considered to address the HVM consideration. The result clearly shows that lower the impedance of baseboard and backplane yields better eye opening at the receiver for the given impedance design range from 85Ω to 100Ω. In other words, 85Ω design on baseboard and backplane is better in performance than 100Ω even if cables, connectors and SAS3 hard disk drives (HDDs) are designed at 100Ω per SAS3 specification.