AES in partially reconfigurable CGRAs

Abstract

Encryption standards demand significant compute capabilities and hence they have often been implemented in FPGAs to satisfy performance requirements. In recent times, coarse grain reconfigurable architectures (CGRA) have become popular for building high throughput applications. In many cases, the regular nature of CGRAs allow the architecture to be clocked at frequencies in excess of 400MHz enabling high throughputs. In this work, we use a model coarse grain reconfigurable fabric to explore the potential of implementing the Advanced Encryption Standard (AES). This coarse grain reconfigurable array with malleable communication links is used to build a multiprocessor archirecture for the highly compute intensive kernel and also exploits dynamic reconfiguration. The semi-systolic near neighbour communication interconnect can be dynamically reconfigured for each “epoch” of computation. Different rounds of the application are computed in different tiles for different blocks of plain text . The paper proposes a radically different implementation of AES where randomization of the computation in each round is achieved which enables us to mitigate the side channel attack vulnerabilities associated with any memory based implementation.