Application of a design for delay testability approach to high speed logic LSIs

Abstract

This paper presents a design for delay testability approach to improve delay fault coverage for high speed logic LSIs. In order to simplify the model for delay test generation from two stage combinational circuit model to ordinary combinational circuit model, we add an extra latch, called sub-latch for each scannable flip-flop. A procedure for delay test generation is also developed to establish high fault coverage. The results for a practical application to logic LSIs used in mainframe computers is given to illustrate the effectiveness of our approach.