Analysis of Semiconductor Process Variations by Means of Hierarchical Median Polish

Abstract

The understanding and controlling of semiconductor process variation is crucial to the performance, functionality and reliability of modern ICs. Due to the complex fabrication process involving hundreds of processing steps, the analysis of the sources of variability is a non-trivial task. In this paper, a novel, simple-to-implement procedure named Hierarchical Median Polish is proposed. The method is designed to decompose the spatial variation of device properties obtained from waferlevel measurements. The decomposition yields non-parametric estimates of the systematic and random variation components on different spatial scales such as wafer-, die- and intra-die level. The practicability of the approach is demonstrated by applying the procedure to wafer-level measurement data of 12100 poly resistors fabricated in a standard CMOS technology.