A 14b threshold configurable dynamically latched comparator for SAR ADCs

Abstract

This paper presents a dynamically latched threshold configurable comparator to eliminate the DAC in conventional SAR ADC designs. The comparator uses intentional circuit asymmetry to generate precise threshold or offset voltages. Four offset stages with resolutions of 15.5 μV, 316 μV, 7.9 mV and 29.85 mV are superimposed to yield a 282.6 mVpp tuning range. The high resolution is obtained by exploiting submicron deviations in device dimensions. The comparator has been designed and tested in 0.13 μm digital CMOS. DC measurements yield 14 bit resolution with 0.38 INL and 0.41 DNL. AC measurements at 6.25 MHz correlate well with the DC measurements. Noise is bandlimited to allow for sampling up to 50 MHz.