Delayed Frontal Solution for Finite-Element based Resistance Extraction

Abstract

To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution method. We show that this method is inefficient when used with a scanline ordering of the elements. As an improvement, we introduce the Delayed Frontal Solution algorithm, which allows us to replace the scanline ordering by the minimumdegree ordering. Thus, extraction times are reduced with more than one order of magnitude at a small cost of extra memory.