Architecture design of a scalable single-chip multi-processor

Abstract

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (M/spl mu/P). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper we explore the main design issues of the architecture platform on which the M/spl mu/P is based.