W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, M. Hossain
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引用次数: 10
Abstract
A 26-32GHz quadrature cascaded phase locked loop (PLL) is presented. The PLL is implemented in 65nm bulk CMOS, consuming 27mW and has less than 100fsec integrated jitter with -114.4 and -112.6dBc/Hz phase noise at 1MHz offset for integer and fractional modes, respectively.
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