Low overhead design for improving hardware trojan detection efficiency

H. Xue, Tyler Moody, Shuo Li, Xiaomeng Zhang, S. Ren
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引用次数: 4

Abstract

Outsourcing of IC fabrication has increased the potential for altering the genuine design with the insertion of concealed circuits (hardware Trojans). A methodology for detecting hardware Trojans (HTs) that has been pursued recently is based on comparing the power and delay response of a genuine chip to the manufactured chip/device under test (DUT). However, the probability of detecting the HT remains small in many cases due to the low probability of activating the concealed circuits. This paper proposes a technique to increase HT activity during testing by inserting probability increase circuits (PICs) at critical points in the design. Preliminary results for a standard HT example show a reduction in time for HT activation of over 95% with modest increases in power, size, and delay overhead.
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低开销设计,提高硬件木马检测效率
集成电路制造的外包增加了通过插入隐藏电路(硬件木马)来改变真实设计的可能性。最近研究的一种检测硬件木马(ht)的方法是基于比较正品芯片和被测制造芯片/设备(DUT)的功率和延迟响应。然而,在许多情况下,由于激活隐藏电路的可能性很低,检测到HT的概率仍然很小。本文提出了一种通过在设计中的关键点插入概率增加电路(PICs)来增加测试过程中HT活性的技术。一个标准HT示例的初步结果表明,HT激活时间减少了95%以上,功率、大小和延迟开销略有增加。
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