Clock separated logic: a double-rail latch circuit technique for high speed digital design

Abstract

A novel configuration, Clock Separated Logic (CSL), for sequential logic circuits which gives complementary outputs for both single-phase clock and two-phase clock equalization logic configuration was developed. The methodology can be applied to static, dynamic latches, D-type flipflops, synchronous counters, and full adders and is appropriate for digital circuit and system designs. In the application of a two-phase 8-bit full adder, it gives improvement over traditional circuits using full swing latches. Analytical model and simulation results proved that a reduction of overall 30% of cycle time is possible in the 8-bit full adder.