A Chip Architecture for Compressive Sensing Based Detection of IC Trojans

Abstract

We present a chip architecture for a compressive sensing based method that can be used in conjunction with the JTAG standard to detect IC Trojans. The proposed architecture compresses chip output resulting from a large number of test vectors applied to a circuit under test (CUT). We describe our designs in sensing leakage power, computing random linear combinations under compressive sensing, and piggybacking these new functionalities on JTAG. Our architecture achieves approximately a 10X speedup and 1000X reduction in output bandwidth while incurring a small area overhead.