autoVHDL: a domain-specific modeling language for the auto-generation of VHDL core wrappers

E. Jones, J. Sprinkle
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引用次数: 3

Abstract

Reconfigurable embedded hardware is a staple of many applications in defense technology and applied engineering. The integration of various embedded hardware "cores" (i.e., the computing units) is complicated by the unintended complexities inherent in the consistent and correct construction of communication pathways - specified using VHDL. This paper presents a domain-specific modeling approach to reducing this complexity. The results include demonstration of the tool, where generated VHDL code with complex data and processing requirements is simulated.
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autoVHDL:用于自动生成VHDL核心包装器的特定于领域的建模语言
可重构嵌入式硬件是国防技术和应用工程中许多应用的主要组成部分。各种嵌入式硬件“核心”(即计算单元)的集成由于通信路径的一致和正确构建(使用VHDL指定)所固有的意想不到的复杂性而变得复杂。本文提出了一种特定于领域的建模方法来降低这种复杂性。结果包括该工具的演示,其中模拟了生成的具有复杂数据和处理需求的VHDL代码。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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