Photolithography Process Improvement for Thick Implant Resist Using 120°C Post-Apply Bake

Abstract

Conventional I-line lithography process utilizes single post-apply bake temperature to unify and simplify the process. As design rule shrinks and mask field size increases, tighter specification is applied on non-critical implant layers, including thick implant resist with thickness typically 4.0 mum and above. Poor uniformity for CD & overlay was observed for thick implant resist layer. Systematic uncorrectable overlay residue was observed from the overlay map. Cross-section analysis shows asymmetric resist profile existed, causing inaccurate signal reading during measurement. Besides, huge amount of resist out-gassing found contaminate the CD-SEM gun tip and causing problem during implant process. In this paper, the problems of thick implant resist layer is analyzed and the process improvement on thick implant resist layer by using higher post-apply bake temperature is introduced. The resist profile changed was checked in detail and the resist removal after implant was verified. As a result, both CD & overlay uniformity was greatly improved. New process with higher post-apply bake condition was fully qualified with comparable wafer yield.