On-Chip Distributed Architectures

Abstract

Currently, the semiconductor industry continues to develop and implement smaller technology nodes, creating the premises for increasingly more powerful applications to find support within the limits of single chip boundaries. Moreover, as technological sizes continue to decrease, interconnect becomes one of the main design constraints, which dominates the power consumption and degrades the performance due to its poor scalability. Thus, some of the major problems in actually delivering complex system-on-chip designs may be identified as: a) global interconnects turn un-manageable (electromigration, voltage drop, on-chip variations, noise constraints etc), interconnect dominates the chip's cost and performance; b) the inability of the designer to track the Moore curve, resulting in "bad" design flows, requiring rework and iteration of design cycles; c) dependability issues caused by effects at submicron technological figures, mixed-signal coupling, availability of pre-designed components to match the specific requirements, etc; d) power consumption, power and clock distribution, scalability. Some of the above problems are tackled by reuse and intellectual property (IP) based design. At the same time, alternative architectures are brought to light, in order to support ever increasing requirements concerning design features like performance, power consumption, adaptability, reusability. In general, these novel architectures try to extract maximum of benefits from current technologies, with respect to the mentioned design characteristics, while also providing a smooth transition to future ones. In this tutorial, we concentrate on two architectural solutions to the above stated challenges. We address issues related to segmented bus and network on-chip systems, starting from motivational background, continuing with technological requirements and possibilities, communication mechanisms, towards design methodologies and application perspectives.