Facet engineered elevated source/drain by selective Si epitaxy for 0.35 micron MOSFETS

Abstract

A novel facet-engineered elevated source/drain formation design is presented. It is found that the ex situ clean prior to selective Si epitaxial growth (SEG) determines the resulting facets on the SEG-source/drain. We show that low angle facets are very advantageous for minimizing parasitic Miller capacitances, while simultaneously grading the source/drain junction near the gate edge and retrieving the source/drain junction from the substrate elsewhere, thus reducing the junction capacitance. Further, we show that both a strong current drive (I/sub DS/) increase and a reduction in parasitic junction capacitance can be realized with facet-engineered phosphorus doped SEG-source/drain with no detrimental effects to short channel device behavior.<>