A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS

Abstract

Integrated in a 0.35 μm 700 V BCD process platform, ultra-low R_{on, sp} 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which R_{on, sp} are 11.5 Ω·mm² and 11.2 Ω·mm², respectively. Utra-low R_{on, sp} benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.