Study of CNTFET Based Pattern Recognition Circuits in Comparison With CMOS Technology

Abstract

Artificial intelligence an integral part of a neural network is based on mathematical equations and artificial neurons. The focus here is to implement 3 bit pattern recognition using CNTFET model in 32nm technology. Its analysis with bulk CMOS technology shows CNTFET based design has better performance in terms of power dissipation, delay and power delay product. This paper aims at analyzing neural network method in pattern recognition. HSPICE level 49 simulations of inverter, current mirror and current mode hamming neural network (HNN) for 3 bit pattern recognition is done. The transient and DC simulation of 3 bit pattern recognition circuit using nano_model_39 CNFET library shows power dissipation same but propagation delays is reduced by 40%. Hence power delay product is improved 100 times using CNTFET.