Surja Sekhar Chakraborty, D. Saravanan, S. Bhawal, K. Hatua
{"title":"Design of an Isolated Gate Driver for Medium Voltage Cascaded H-Bridge (CHB) Based Solid State Transformer (SST)","authors":"Surja Sekhar Chakraborty, D. Saravanan, S. Bhawal, K. Hatua","doi":"10.1109/GlobConPT57482.2022.9938157","DOIUrl":null,"url":null,"abstract":"The design of an isolated gate driver for a Medium Voltage (MV) Cascaded H-bridge (CHB) converter is proposed in this paper. Isolation with proper electrical insulation and a low common-mode coupling capacitance are considered as the primary design criteria while designing the gate driver. A detailed circuit analysis has been carried out to find the isolation issues in the MV CHB converters, which necessitates a 2ndstage of isolation in the gate driver circuit. Apart from improving the isolation voltage level, the additional isolation stage helps to reduce the coupling capacitance in the common mode path. As the device count for an MV CHB converter is significantly high, the complementary pulses have been generated locally in a CPLD-based delay card, which reduces the count of the optical cables and the associated components. It helps to make the system simple and cost effective. Finally, the design of the proposed gate drivers and associated delay cards are verified in a hardware prototype of 1.65kV/300V, 10kVA Solid State Transformer (SST).","PeriodicalId":431406,"journal":{"name":"2022 IEEE Global Conference on Computing, Power and Communication Technologies (GlobConPT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Global Conference on Computing, Power and Communication Technologies (GlobConPT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GlobConPT57482.2022.9938157","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The design of an isolated gate driver for a Medium Voltage (MV) Cascaded H-bridge (CHB) converter is proposed in this paper. Isolation with proper electrical insulation and a low common-mode coupling capacitance are considered as the primary design criteria while designing the gate driver. A detailed circuit analysis has been carried out to find the isolation issues in the MV CHB converters, which necessitates a 2ndstage of isolation in the gate driver circuit. Apart from improving the isolation voltage level, the additional isolation stage helps to reduce the coupling capacitance in the common mode path. As the device count for an MV CHB converter is significantly high, the complementary pulses have been generated locally in a CPLD-based delay card, which reduces the count of the optical cables and the associated components. It helps to make the system simple and cost effective. Finally, the design of the proposed gate drivers and associated delay cards are verified in a hardware prototype of 1.65kV/300V, 10kVA Solid State Transformer (SST).