{"title":"Bounding worst-case instruction cache performance","authors":"R. Arnold, F. Mueller, D. Whalley, M. Harmon","doi":"10.1109/REAL.1994.342718","DOIUrl":null,"url":null,"abstract":"The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently unpredictable, since the behavior of a cache reference depends upon the history of the previous references. The use of caches is only suitable for real-time systems if a reasonably tight bound on the performance of programs using cache memory can be predicted. This paper describes an approach for bounding the worst-case instruction cache performance of large code segments. First, a new method called static cache simulation is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. A timing analyzer, which uses the categorization information, then estimates the worst-case instruction cache performance for each loop and function in the program.<<ETX>>","PeriodicalId":374952,"journal":{"name":"1994 Proceedings Real-Time Systems Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"260","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1994 Proceedings Real-Time Systems Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/REAL.1994.342718","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 260
Abstract
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently unpredictable, since the behavior of a cache reference depends upon the history of the previous references. The use of caches is only suitable for real-time systems if a reasonably tight bound on the performance of programs using cache memory can be predicted. This paper describes an approach for bounding the worst-case instruction cache performance of large code segments. First, a new method called static cache simulation is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. A timing analyzer, which uses the categorization information, then estimates the worst-case instruction cache performance for each loop and function in the program.<>