Bounding worst-case instruction cache performance

R. Arnold, F. Mueller, D. Whalley, M. Harmon
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引用次数: 260

Abstract

The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently unpredictable, since the behavior of a cache reference depends upon the history of the previous references. The use of caches is only suitable for real-time systems if a reasonably tight bound on the performance of programs using cache memory can be predicted. This paper describes an approach for bounding the worst-case instruction cache performance of large code segments. First, a new method called static cache simulation is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. A timing analyzer, which uses the categorization information, then estimates the worst-case instruction cache performance for each loop and function in the program.<>
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限定最坏情况下的指令缓存性能
对于实时系统的架构师来说,使用缓存是一个困难的权衡。虽然缓存提供了显著的性能优势,但它们也被视为本质上不可预测的,因为缓存引用的行为取决于以前引用的历史记录。如果可以预测使用缓存的程序的性能有一个合理的严格限制,那么缓存的使用只适合于实时系统。本文描述了一种限定大代码段最坏情况下指令缓存性能的方法。首先,采用静态缓存模拟的方法分析程序控制流,对每条指令的缓存行为进行静态分类。时序分析器使用分类信息,然后估计程序中每个循环和函数的最坏情况指令缓存性能
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