P. Tzeng, Y. Hsin, Jui-Chin Chen, Shang-Chun Chen, Chien-Ying Wu, W. Tsai, Chung-Chih Wang, C. Ho, Chien-Chou Chen, Y. Hsu, S. Shen, S. Liao, C. Chien, Hsiang-Hung Chang, Cha-Hsin Lin, T. Ku, M. Kao
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引用次数: 3
Abstract
Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules are also provided as process guidelines.
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