An improved heuristic for optimizing SI memory cells application: a fully optimized SI class AB grounded gate cell

Abstract

Optimally designing switched current (SI) memory cells is a very tedious process. In addition, it is usually limited to the design of ideal cells. Thus, in this paper, we deal with fully optimizing these cells and particularly real cells. Since SI class AB grounded gate memory cells are well known to be improved cells, we applied the proposed heuristic to design these cells. Also, besides maximizing performances and minimizing famous error sources, we focus on optimally sizing transistors forming switches and bias currents. The optimization procedure, developed in C++ software, allows automatic design of the cell. It is also highlighted in the followings. The cell designed with the use of CMOS 0.35 /spl mu/m process under a single 3.3 V power voltage supply, achieves more than 83.6 dB as a dynamic range and reaches less than 3.5 ns as settling time.