Performance Evaluation and Comparison and Improvement of Standard Cell Placement Techniques in VLSI Design

Abstract

Heuristic approach is preferred as a solution to optimization of Non-Deterministic Polynomial hard (NP-hard) problems of sizes that are nontrivial because of speed limitations of exact optimization methods. This paper, therefore, proposes to investigate recent heuristic techniques for solving the standard cell placement problems at physical design stage of VLSI design cycle. The techniques considered are Simulated Annealing (SA), Hopfield Neural Network and Genetic Algorithm (GA). In addition to individual studies of the methods, we compare them in terms of solution quality and computing speed in connection with the standard cell placement problems. Finally we shall suggest a method to enhance them using Memetic Algorithms (MA).