{"title":"Threshold Voltage Extraction Using Static NBTI Aging","authors":"Puneet Ramesh Savanur, S. Tragoudas","doi":"10.1109/DFT.2018.8602814","DOIUrl":null,"url":null,"abstract":"A novel approach to extract the threshold voltage of a pMOS transistor in a tile of the integrated circuit is proposed. Low voltage is applied to the transistor for a predetermined time period and then its delay due to static negative bias temperature instability aging is measured. Experimental results in 45nm technology show that the proposed approach extracts the threshold voltage with very high resolution.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2018.8602814","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A novel approach to extract the threshold voltage of a pMOS transistor in a tile of the integrated circuit is proposed. Low voltage is applied to the transistor for a predetermined time period and then its delay due to static negative bias temperature instability aging is measured. Experimental results in 45nm technology show that the proposed approach extracts the threshold voltage with very high resolution.
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