Self consistent simulation for C-V characterization of sub 10nm Tri-Gate and Double Gate SOI FinFETs incorporating quantum mechanical effects

Abstract

Capacitance-Voltage (C-V) characteristics of Tri-Gate (TG) and Double Gate (DG) Silicon-on-Insulator (SOI) FinFETs having sub 10nm dimensions are obtained by self consistent method using coupled Schrodinger-Poisson solver taking into account quantum mechanical effects. Though self-consistent simulation to determine current and other short channel effects in these devices have been demonstrated in recent literature, C-V characterization is yet to be done using self-consistent method. We investigate here the C-V characteristics of the devices with the variation of an important process parameter, the silicon film thickness. The gate inversion capacitance should be higher in TG FinFET than that of DG FinFET because of the presence of thick oxide layer under the top gate of DG FinFET. Simulation results validate this phenomenon with an indication that drive current tends to increase with an increase in the number of gates.