A high linearity compact timing vernier for CMOS timing generator

Abstract

We have developed a novel timing vernier for a high integration CMOS timing generator of Automatic Test Equipment (ATE). To reduce area and power, the proposed timing vernier utilizes the charge injection architecture. An 893ps span, 7ps resolution timing vernier is fabricated in a 0.18µm CMOS process. We achieved a linearity error of 4.2ps pp without calibration. The timing vernier occupies an area of 0.042mm2 and dissipates a power of 16mW from a 1.8V supply at an operating frequency of 373MHz. Using this timing vernier, we realized a 1.12Gbps timing generator. The chip size is 6.2 × 6.2mm2. It consumes 2.1W from a 1.8V supply. The temperature coefficient and the supply voltage dependency are +2.0ps/°C, −0.2ps/mV respectively. The timing jitter is 17ps pp.