Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology

Abstract

In this paper, we present a study of the effects of strained contact etch stop layer on 65 nm CMOS transistor performance. It is found that the nitride layer above the transistor can improve the transistor drive current by 8.5% for NMOS and 6% for PMOS. By combining a complete electrical analysis, mechanical modeling and quantum simulations, we have obtained a detailed understanding of how transistor layout rules influence the strain enhancements.