Novel ESD protection design methodology and latchup prevention for a 0.5-/spl mu/m CMOS ASIC library

Abstract

In this paper, instead of the traditional experience-based trial-and-error ESD design approach, a novel ESD protection design methodology is proposed, which resolves the costly and time-consuming problems of high-performance ESD protection development in deep-submicron CMOS technology. And this novel design method is conducted and verified in a 0.5-mum CMOS technology to accomplish I/O cell design of a CMOS ASIC library, whose human-body-model ESD level can be great than 4.5kV. To effectively improve latchup free capability, latchup prevention design is also discussed