Data stability enhancement techniques for nanoscale memory circuits: 7T memory design tradeoffs and options in 80nm UMC CMOS technology

Abstract

SRAM data stability and leakage currents are major concerns in nanometer CMOS technologies. The primary design challenge related to the conventional six-transistor (6T) memory cells is the conflicting set of requirements for achieving read data stability and write ability. A seven-transistor (7T) SRAM cell provides enhanced data stability by isolating the bitlines from data storage nodes during a read operation. The design tradeoffs in a 7T SRAM cell are explored in this paper with a UMC 80nm multi-threshold-voltage CMOS technology that provides a rich set of device options. An electrical performance metric is proposed to evaluate and compare the memory circuits. The multi-threshold-voltage SRAM circuits offering the highest data stability, widest write margin, smallest read and write power consumption, and lowest leakage currents are identified.