Design Of Wallace Multiplier Using Novel Approximate 4:2 Compressors

Abstract

In this study, we suggested an approximation multiplier that employs an approximate 4-2 compressor and is energy-efficient. When compared to the current designs, the suggested compressor has a small area. The results of simulations reveal that the suggested approximation multipliers display a reasonable decrease in Mean Error Distance, Mean Relative Error Distance, Normalized Mean Error Distance, compared to multiplier that is designed with exact compressors. The Power, Delay and Area of multipliers developed with this approximate compressor is superior to that obtained with previously suggested approximate compressors, according to implementation results in 90nm CMOS technology.