{"title":"Design and optimization of networked wireless information systems","authors":"Mani Srivastava, Ee","doi":"10.1109/IWV.1998.667119","DOIUrl":null,"url":null,"abstract":"As entire systems are being integrated on a single chip, the chip designers are in effect becoming the system designers. However, it is an open question whether the board-level system architecture design and optimization methodologies are also well-suited for such system-chips. Our experience with the networked wireless multimedia nodes and devices being designed under UCLA's MERLIN project shows that the system-chip design problem is not just one of complexity and scalability arising from a large number of transistors. Instead, the primary problem and opportunity is in managing the diversity in a system, and exploiting it to optimize the system architecture. Indeed, the ability to do design tradeoffs and optimizations across diverse system layers and functions being integrated on a die is crucial. Facilitating such system level optimization ought to be the focus of design automation tools, and not the mere integration of cores encapsulating intellectual property. Supporting \"tall and thin\" chip designers is no longer adequate. The tools for system-chip design have to support \"tall and fat\" designers who, for example, need to optimize across the radio, protocol, DSP, and microcontroller functions in a wireless system-chip.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWV.1998.667119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
As entire systems are being integrated on a single chip, the chip designers are in effect becoming the system designers. However, it is an open question whether the board-level system architecture design and optimization methodologies are also well-suited for such system-chips. Our experience with the networked wireless multimedia nodes and devices being designed under UCLA's MERLIN project shows that the system-chip design problem is not just one of complexity and scalability arising from a large number of transistors. Instead, the primary problem and opportunity is in managing the diversity in a system, and exploiting it to optimize the system architecture. Indeed, the ability to do design tradeoffs and optimizations across diverse system layers and functions being integrated on a die is crucial. Facilitating such system level optimization ought to be the focus of design automation tools, and not the mere integration of cores encapsulating intellectual property. Supporting "tall and thin" chip designers is no longer adequate. The tools for system-chip design have to support "tall and fat" designers who, for example, need to optimize across the radio, protocol, DSP, and microcontroller functions in a wireless system-chip.