Digital design tools such as logic synthesis, semicustom layout and behavioral simulation have drastically changed the digital IC design process, enabling design of complex "systems on a chip". The usefulness of such chips are limited in a world dominated by information that is not represented by 0's and 1's. Overcoming these limitations has led to mixed-signal, and mixed-domain technologies. We focus on design methodologies and tools to aid the design of complex microelectromechanical systems (MEMS) having large numbers of mixed-domain components. We propose a hierarchically structured design approach that is compatible with standard IC design involving a schematic approach to MEMS design, a layout synthesis strategy for cell-level design automation, and a feature-recognition based device extractor for layout verification. We present emerging results on our design methodology and tools.
{"title":"Design methodology for mixed-domain systems-on-a-chip [MEMS design]","authors":"T. Mukherjee, G. Fedder","doi":"10.1109/IWV.1998.667129","DOIUrl":"https://doi.org/10.1109/IWV.1998.667129","url":null,"abstract":"Digital design tools such as logic synthesis, semicustom layout and behavioral simulation have drastically changed the digital IC design process, enabling design of complex \"systems on a chip\". The usefulness of such chips are limited in a world dominated by information that is not represented by 0's and 1's. Overcoming these limitations has led to mixed-signal, and mixed-domain technologies. We focus on design methodologies and tools to aid the design of complex microelectromechanical systems (MEMS) having large numbers of mixed-domain components. We propose a hierarchically structured design approach that is compatible with standard IC design involving a schematic approach to MEMS design, a layout synthesis strategy for cell-level design automation, and a feature-recognition based device extractor for layout verification. We present emerging results on our design methodology and tools.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As entire systems are being integrated on a single chip, the chip designers are in effect becoming the system designers. However, it is an open question whether the board-level system architecture design and optimization methodologies are also well-suited for such system-chips. Our experience with the networked wireless multimedia nodes and devices being designed under UCLA's MERLIN project shows that the system-chip design problem is not just one of complexity and scalability arising from a large number of transistors. Instead, the primary problem and opportunity is in managing the diversity in a system, and exploiting it to optimize the system architecture. Indeed, the ability to do design tradeoffs and optimizations across diverse system layers and functions being integrated on a die is crucial. Facilitating such system level optimization ought to be the focus of design automation tools, and not the mere integration of cores encapsulating intellectual property. Supporting "tall and thin" chip designers is no longer adequate. The tools for system-chip design have to support "tall and fat" designers who, for example, need to optimize across the radio, protocol, DSP, and microcontroller functions in a wireless system-chip.
{"title":"Design and optimization of networked wireless information systems","authors":"Mani Srivastava, Ee","doi":"10.1109/IWV.1998.667119","DOIUrl":"https://doi.org/10.1109/IWV.1998.667119","url":null,"abstract":"As entire systems are being integrated on a single chip, the chip designers are in effect becoming the system designers. However, it is an open question whether the board-level system architecture design and optimization methodologies are also well-suited for such system-chips. Our experience with the networked wireless multimedia nodes and devices being designed under UCLA's MERLIN project shows that the system-chip design problem is not just one of complexity and scalability arising from a large number of transistors. Instead, the primary problem and opportunity is in managing the diversity in a system, and exploiting it to optimize the system architecture. Indeed, the ability to do design tradeoffs and optimizations across diverse system layers and functions being integrated on a die is crucial. Facilitating such system level optimization ought to be the focus of design automation tools, and not the mere integration of cores encapsulating intellectual property. Supporting \"tall and thin\" chip designers is no longer adequate. The tools for system-chip design have to support \"tall and fat\" designers who, for example, need to optimize across the radio, protocol, DSP, and microcontroller functions in a wireless system-chip.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130610478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The ever-increasing complexity of electronic systems makes it imperative to develop effective systems level design automation languages, methodologies, and tools. Commercial systems face increasing complexity and performance requirements, while achieving decreasing times to market and maximizing profits despite shrinking product life-cycles. Defense systems face similar issues, but must also support life cycles which span years or decades, thus requiring redesign, support or prevention of parts obsolescence challenges. For cost-effective development of systems in this context, design teams need to exploit the best commercial and defense design practices and adapt them as needed to also support concurrent engineering considerations. This paper explores requirements for the emerging system level design language and the methodological needs for it to support multi-disciplinary design, including hardware software co-design, mechanical and packaging support, concurrent engineering, test, and related issues.
{"title":"Language-based electronics systems design automation","authors":"G. D. Peterson","doi":"10.1109/IWV.1998.667137","DOIUrl":"https://doi.org/10.1109/IWV.1998.667137","url":null,"abstract":"The ever-increasing complexity of electronic systems makes it imperative to develop effective systems level design automation languages, methodologies, and tools. Commercial systems face increasing complexity and performance requirements, while achieving decreasing times to market and maximizing profits despite shrinking product life-cycles. Defense systems face similar issues, but must also support life cycles which span years or decades, thus requiring redesign, support or prevention of parts obsolescence challenges. For cost-effective development of systems in this context, design teams need to exploit the best commercial and defense design practices and adapt them as needed to also support concurrent engineering considerations. This paper explores requirements for the emerging system level design language and the methodological needs for it to support multi-disciplinary design, including hardware software co-design, mechanical and packaging support, concurrent engineering, test, and related issues.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130432941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Our present ability to work with video has been confined to a wired environment, requiring both the video encoder and decoder to be physically connected to a power supply and a wired communication link. This paper presents two design examples for delivering high-quality image and video data in a wireless environment. The first example is a wireless video-on-demand system and the second example is a single-chip digital camera. The discussion will focus on the architectural and circuit design techniques developed specifically for silicon integration of high-performance, low-power wireless video systems.
{"title":"Wireless video systems","authors":"T. Meng","doi":"10.1109/IWV.1998.667110","DOIUrl":"https://doi.org/10.1109/IWV.1998.667110","url":null,"abstract":"Our present ability to work with video has been confined to a wired environment, requiring both the video encoder and decoder to be physically connected to a power supply and a wired communication link. This paper presents two design examples for delivering high-quality image and video data in a wireless environment. The first example is a wireless video-on-demand system and the second example is a single-chip digital camera. The discussion will focus on the architectural and circuit design techniques developed specifically for silicon integration of high-performance, low-power wireless video systems.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121018192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The defining characteristic of ubiquitous computing is the attempt to break away from the traditional desktop computing paradigm and move computational power into the environment that surrounds the user. Increasing miniaturization brought on by advances in areas such as VLSI design means that we will soon be able to instrument our environments in order to realize the dream of ubiquitous computing. The promise of ubiquitous computing, however, is that the increased pervasiveness of computation will lead to less intrusive and more valuable services to the end user. For this dream to be realized we need to accompany hardware advances with advances in software technology. In this paper, the author discusses some software challenges for ubiquitous computing.
{"title":"Software design issues for ubiquitous computing","authors":"G. Abowd","doi":"10.1109/IWV.1998.667131","DOIUrl":"https://doi.org/10.1109/IWV.1998.667131","url":null,"abstract":"The defining characteristic of ubiquitous computing is the attempt to break away from the traditional desktop computing paradigm and move computational power into the environment that surrounds the user. Increasing miniaturization brought on by advances in areas such as VLSI design means that we will soon be able to instrument our environments in order to realize the dream of ubiquitous computing. The promise of ubiquitous computing, however, is that the increased pervasiveness of computation will lead to less intrusive and more valuable services to the end user. For this dream to be realized we need to accompany hardware advances with advances in software technology. In this paper, the author discusses some software challenges for ubiquitous computing.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116591534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present our view of the high-level timing issues in the design and validation of embedded real-time systems. We first define the derivation problem: the problem of deriving internal timing constraints from external timing constraints in an embedded real-time system. We then give a comprehensive classification of timing constraints, discuss the state of the art on high-level system modeling and on the timing constraint derivation techniques. We finally give some pointers for future research.
{"title":"Timing issues in system-level design","authors":"Ali Dasdan, Rajesh Gupta","doi":"10.1109/IWV.1998.667136","DOIUrl":"https://doi.org/10.1109/IWV.1998.667136","url":null,"abstract":"We present our view of the high-level timing issues in the design and validation of embedded real-time systems. We first define the derivation problem: the problem of deriving internal timing constraints from external timing constraints in an embedded real-time system. We then give a comprehensive classification of timing constraints, discuss the state of the art on high-level system modeling and on the timing constraint derivation techniques. We finally give some pointers for future research.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124953332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P.H.A. van der Putten, J. Voeten, M. Geilen, M. Stevens
There are many fundamental problems in the design of object-oriented methods that support the development of formal executable models on a system level, and that are suitable for hardware/software co-specification. System level description formalisms should combine concepts expressive enough to model the essentials of a system on the right level of abstraction. This paper reports experiences in developing a specification and design method SHE (Software/Hardware Engineering) which is based on a formal language POOSL (Parallel Object-Oriented Specification Language). The method offers a path from an informal specification to a unified formal model that enables evaluation of system properties. This paper describes concrete new results as well as an approach towards research on system level methodology.
{"title":"System level design methodology","authors":"P.H.A. van der Putten, J. Voeten, M. Geilen, M. Stevens","doi":"10.1109/IWV.1998.667107","DOIUrl":"https://doi.org/10.1109/IWV.1998.667107","url":null,"abstract":"There are many fundamental problems in the design of object-oriented methods that support the development of formal executable models on a system level, and that are suitable for hardware/software co-specification. System level description formalisms should combine concepts expressive enough to model the essentials of a system on the right level of abstraction. This paper reports experiences in developing a specification and design method SHE (Software/Hardware Engineering) which is based on a formal language POOSL (Parallel Object-Oriented Specification Language). The method offers a path from an informal specification to a unified formal model that enables evaluation of system properties. This paper describes concrete new results as well as an approach towards research on system level methodology.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130219728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent experiments for the realisation of data-dominated multi-media applications have clearly demonstrated that the main power (and largely also area) cost is situated in the memory units and the (bus) communication hardware. On the custom hardware side, several system level memory management related methodologies are being proposed which promise very large savings on power and also on area while still meeting the real-time constraints. Unfortunately, on the software side these methodologies are not applicable as such. In order to alleviate this situation for systems-on-a-chip with a heterogeneous mix of processors, novel methodology and architecture approaches are required. In this research summary paper, the currently available solutions are reviewed and some major problems to be solved in the future are identified.
{"title":"Power-efficient data storage and transfer methodologies: Current solutions and remaining problems","authors":"F. Catthoor","doi":"10.1109/IWV.1998.667115","DOIUrl":"https://doi.org/10.1109/IWV.1998.667115","url":null,"abstract":"Recent experiments for the realisation of data-dominated multi-media applications have clearly demonstrated that the main power (and largely also area) cost is situated in the memory units and the (bus) communication hardware. On the custom hardware side, several system level memory management related methodologies are being proposed which promise very large savings on power and also on area while still meeting the real-time constraints. Unfortunately, on the software side these methodologies are not applicable as such. In order to alleviate this situation for systems-on-a-chip with a heterogeneous mix of processors, novel methodology and architecture approaches are required. In this research summary paper, the currently available solutions are reviewed and some major problems to be solved in the future are identified.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116544611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IFSys is an integrated system-level synthesis framework which allows a complete computer system to be specified using a set of high-level building blocks rather than behavioral level specifications. By reusing domain-specific design knowledge, alternative hardware and software configurations can be rapidly specified and synthesized. Thirty-two different embedded computer systems were synthesized using IFSys which spanned a factor of 1.5 in cost, 1.2 in power 2.2 in area, 1.5 in program size, and 21 in performance.
{"title":"IFSys: an integrated framework for system-level synthesis","authors":"J. Deang, G. McNally, D. Siewiorek","doi":"10.1109/IWV.1998.667106","DOIUrl":"https://doi.org/10.1109/IWV.1998.667106","url":null,"abstract":"IFSys is an integrated system-level synthesis framework which allows a complete computer system to be specified using a set of high-level building blocks rather than behavioral level specifications. By reusing domain-specific design knowledge, alternative hardware and software configurations can be rapidly specified and synthesized. Thirty-two different embedded computer systems were synthesized using IFSys which spanned a factor of 1.5 in cost, 1.2 in power 2.2 in area, 1.5 in program size, and 21 in performance.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127750085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Energy efficiency is crucial for wireless networks due to the limited battery life of mobile terminals. Power conservation techniques are commonly used in the hardware design of such systems. In addition, a low-power design of the entire protocol stack of wireless systems can significantly enhance energy efficiency and network utilization. This paper discusses recent advances and contributes novel ideas on power adaptive design of networking protocols.
{"title":"Energy conservation design techniques for mobile wireless VLSI systems","authors":"Prathima Agrawal","doi":"10.1109/IWV.1998.667111","DOIUrl":"https://doi.org/10.1109/IWV.1998.667111","url":null,"abstract":"Energy efficiency is crucial for wireless networks due to the limited battery life of mobile terminals. Power conservation techniques are commonly used in the hardware design of such systems. In addition, a low-power design of the entire protocol stack of wireless systems can significantly enhance energy efficiency and network utilization. This paper discusses recent advances and contributes novel ideas on power adaptive design of networking protocols.","PeriodicalId":185325,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121074176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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