Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors

Abstract

Recent advances in CMOS technology adds more transistors to the chip that are utilised for improving processing capability by adding multiple processing components. These multiple cores raise the data demands leading to larger on-chip caches. Together, these add to the energy consumption as well as heat dissipation. Increase in chip temperature requires efficient cooling mechanisms as high temperatures can damage the onchip circuitry. Thus, the performance enhancement comes at the cost of higher power budget as well as temperature. Large onchip caches occupy significant area of the chip and are major contributors to leakage energy. It is known that as technology scales leakage becomes a prominent component which also affects the chip temperature. This paper aims to control the chip temperature by controlling the leakage energy dissipated by the last level caches (LLCs). Towards this we propose a hybrid LLC that uses a combination of SRAM cache banks and non-volatile memory (NVM) technology based STT-RAM banks. STT-RAM technology has the advantage of high density and low leakage.We demonstrate that low-leakage STT-RAM banks help in reducing the temperature of the tile in which they are located and it also assists in reducing the average chip temperature. Experimental evaluation on an isoarea and iso-capacity architecture that uses a hybrid LLC shows reduction the average chip temperature as well as gives gains in static energy and EDP compared to baseline architecture.