A new reuse method of analog circuit design for CMOS technology migration

Abstract

In this paper, a new method for analog design reuse during technology migration is proposed. Previous works ignore the variance of technology parameters. Accordingly, bases on gm/id methodology and ACM model, our methodology adopts an extra pre-extraction step for parameters deciding. This enables a practical description of MOS transistor working state and is therefore more precisely in deciding the design freedoms of two typical strategies. The methodology is validated and results are compared with a common-source amplifier from 0.6um to 0.35um technology.