Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

Abstract

For the demand of sever systems with high performance, high density and low power consumption, 3-D DDR4 SDRAM with TSVs was developed. In order to achieve higher data rate at lower voltage in comparison with precedent DDR3 SDRAM with TSVs, the placements of TSVs have been optimized without the penalty of chip size and the calibration method for reducing process mismatch between stacked DRAM chips is proposed. Additionally, new cell test method for stacked dies is adopted to keep costs down and the skewed self-refresh is proposed to reduce power noise. The IO speed of new DDR4 SDRAM with TSVs is increased to 2.4Gb/s at 1.2V.