Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858402
Quan Pan, Zhengxiong Hou, Yipeng Wang, Yan Lu, W. Ki, Keh-Chung Wang, C. Yue
A 65-nm CMOS monolithic optical receiver IC with on-chip photodetector (PD) using the p-well/deep-n-well (PW/DNW) junction is presented for short-range optical communication using 850-nm wavelength. An adaptive continuous-time linear equalizer (CTLE) with 33-dB tunable gain is employed to compensate for the limited PD responsivity and bandwidth. For 850-nm optical PRBS-15 inputs, the receiver achieves record data rates and efficiencies of 9 Gb/s at 5.35 pJ/bit and 18 Gb/s at 2.7 pJ/bit with the PD biased in 0.5-V standard mode and 12.3-V avalanche mode, respectively. The core chip occupies 0.23 mm2 and consumes 48 mW.
{"title":"A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer","authors":"Quan Pan, Zhengxiong Hou, Yipeng Wang, Yan Lu, W. Ki, Keh-Chung Wang, C. Yue","doi":"10.1109/VLSIC.2014.6858402","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858402","url":null,"abstract":"A 65-nm CMOS monolithic optical receiver IC with on-chip photodetector (PD) using the p-well/deep-n-well (PW/DNW) junction is presented for short-range optical communication using 850-nm wavelength. An adaptive continuous-time linear equalizer (CTLE) with 33-dB tunable gain is employed to compensate for the limited PD responsivity and bandwidth. For 850-nm optical PRBS-15 inputs, the receiver achieves record data rates and efficiencies of 9 Gb/s at 5.35 pJ/bit and 18 Gb/s at 2.7 pJ/bit with the PD biased in 0.5-V standard mode and 12.3-V avalanche mode, respectively. The core chip occupies 0.23 mm2 and consumes 48 mW.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127188711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858427
Changhyuk Lee, Ben Johnson, A. Molnar
We present a 72×60, angle-sensitive single photon avalanche diode (A-SPAD) array, able to perform lens-less 3-D fluorescent lifetime imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, reject high-powered UV stimulus, and map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings over the SPAD to extract the incident angle of light, enabling 3-D localization at a micrometer scale. The chip integrates pixel-level counters and shared timing circuitry, and is implemented in unmodified 180nm CMOS.
{"title":"An on-chip 72×60 angle-sensitive single photon image sensor array for lens-less time-resolved 3-D fluorescence lifetime imaging","authors":"Changhyuk Lee, Ben Johnson, A. Molnar","doi":"10.1109/VLSIC.2014.6858427","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858427","url":null,"abstract":"We present a 72×60, angle-sensitive single photon avalanche diode (A-SPAD) array, able to perform lens-less 3-D fluorescent lifetime imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, reject high-powered UV stimulus, and map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings over the SPAD to extract the incident angle of light, enabling 3-D localization at a micrometer scale. The chip integrates pixel-level counters and shared timing circuitry, and is implemented in unmodified 180nm CMOS.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125508100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858383
Yi-Lin Tsai, Jian-You Chen, B. Wang, Tzu-Yu Yeh, Tsung-Hsien Lin
A 400MHz 10Mbps differential BPSK (D-BPSK) receiver (RX) is presented. This RX adopts a proposed reference-less dynamic phase-to-amplitude demodulation scheme, which converts signal phase transition to distinct amplitude variation. The proposed RX can support a data rate up to 10Mbps. It achieves -63dBm sensitivity at 0.1% BER and draws 1.77mW in 0.18μm CMOS.
{"title":"A 400MHz 10Mbps D-BPSK receiver with a reference-less dynamic phase-to-amplitude demodulation technique","authors":"Yi-Lin Tsai, Jian-You Chen, B. Wang, Tzu-Yu Yeh, Tsung-Hsien Lin","doi":"10.1109/VLSIC.2014.6858383","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858383","url":null,"abstract":"A 400MHz 10Mbps differential BPSK (D-BPSK) receiver (RX) is presented. This RX adopts a proposed reference-less dynamic phase-to-amplitude demodulation scheme, which converts signal phase transition to distinct amplitude variation. The proposed RX can support a data rate up to 10Mbps. It achieves -63dBm sensitivity at 0.1% BER and draws 1.77mW in 0.18μm CMOS.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858416
T. Tsukizawa, Atsushi Yoshimoto, H. Komori, K. Miyanaga, R. Kitamura, Y. Morishita, M. Irie, Yoichi Nagaso, Takeaki Watanabe, K. Takinami, N. Saito
A PVT tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad is presented. By introducing a newly proposed self-sensing LDO, the transceiver adjusts bias currents and the LDO output voltage for the PA to minimize the output power variation while relaxing the hot carrier injection (HCI) degradation. The measurement shows excellent robustness against PVT variations, demonstrating only 5 dB output power variation over -20 °C to 85 °C across process corners.
{"title":"A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad","authors":"T. Tsukizawa, Atsushi Yoshimoto, H. Komori, K. Miyanaga, R. Kitamura, Y. Morishita, M. Irie, Yoichi Nagaso, Takeaki Watanabe, K. Takinami, N. Saito","doi":"10.1109/VLSIC.2014.6858416","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858416","url":null,"abstract":"A PVT tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad is presented. By introducing a newly proposed self-sensing LDO, the transceiver adjusts bias currents and the LDO output voltage for the PA to minimize the output power variation while relaxing the hot carrier injection (HCI) degradation. The measurement shows excellent robustness against PVT variations, demonstrating only 5 dB output power variation over -20 °C to 85 °C across process corners.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115062947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858411
S. Tanaka, Y. Ishii, M. Yabuuchi, T. Sano, Koji Tanaka, Y. Tsukamoto, K. Nii, Hirotoshi Sato
We propose a partially write-assisted two read/write dual-port (DP) SRAM in 28-nm technology. Our write-assist circuit with metal-coupled capacitance can generate negative bitline bias which is flexibly adjustable to any bit-word configurations. By effectively applying assist biases only to sub-blocks with margin-less bits, power overhead can be reduced with Vmin improved. A test chip including proposed 512-kb DP SRAM macro is designed using 28-nm HKMG technology, from which we successfully observed 1-GHz operation at 1.0 V, 190 mV Vmin improvement, and 21% power reduction compared to a conventional assist.
{"title":"A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline","authors":"S. Tanaka, Y. Ishii, M. Yabuuchi, T. Sano, Koji Tanaka, Y. Tsukamoto, K. Nii, Hirotoshi Sato","doi":"10.1109/VLSIC.2014.6858411","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858411","url":null,"abstract":"We propose a partially write-assisted two read/write dual-port (DP) SRAM in 28-nm technology. Our write-assist circuit with metal-coupled capacitance can generate negative bitline bias which is flexibly adjustable to any bit-word configurations. By effectively applying assist biases only to sub-blocks with margin-less bits, power overhead can be reduced with Vmin improved. A test chip including proposed 512-kb DP SRAM macro is designed using 28-nm HKMG technology, from which we successfully observed 1-GHz operation at 1.0 V, 190 mV Vmin improvement, and 21% power reduction compared to a conventional assist.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122459003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A multi-mode Low-Density Parity-Check (LDPC) error correction engine with a Digital Signal Processing (DSP) module is presented for low power and ultra high reliability NAND Flash memory controllers. The DSP module improves the reliability of the storage systems via calculating the adaptive reliability information and translating the information into Log-Likelihood Ratio (LLR) for soft bit decoding. According to the experiment results on sub-20nm Triple Level per Cell (TLC) NAND Flash memory, the retention ability of LDPC with DSP is a 20 times improvement over BCH code and 2 to 5 times improvement over conventional LDPC. Moreover, the proposed decoder reaches a throughput over 400MB/s as well as a power consumption of 21.8mW under 40nm CMOS technology at 45 bit errors.
{"title":"A low power and ultra high reliability LDPC error correction engine with Digital Signal Processing for embedded NAND Flash Controller in 40nm COMS","authors":"Wei Lin, Shao-Wei Yen, Yu-Cheng Hsu, Yu-Hsiang Lin, L. Liang, Tien-Ching Wang, Pei-Yu Shih, Kuo-Hsin Lai, Kuo-Yi Cheng, Chun-Yen Chang","doi":"10.1109/VLSIC.2014.6858405","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858405","url":null,"abstract":"A multi-mode Low-Density Parity-Check (LDPC) error correction engine with a Digital Signal Processing (DSP) module is presented for low power and ultra high reliability NAND Flash memory controllers. The DSP module improves the reliability of the storage systems via calculating the adaptive reliability information and translating the information into Log-Likelihood Ratio (LLR) for soft bit decoding. According to the experiment results on sub-20nm Triple Level per Cell (TLC) NAND Flash memory, the retention ability of LDPC with DSP is a 20 times improvement over BCH code and 2 to 5 times improvement over conventional LDPC. Moreover, the proposed decoder reaches a throughput over 400MB/s as well as a power consumption of 21.8mW under 40nm CMOS technology at 45 bit errors.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130608263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858439
Q. Khan, S. Kim, Mrunmay Talegaonkar, A. Elshazly, A. Rao, Nathanael Griesert, Greg Winter, W. McIntyre, P. Hanumolu
A time-based PID compensator that combines the advantages of both analog and digital controllers is used to implement a high frequency low quiescent current buck converter. Fabricated in 180nm CMOS process, the proposed buck converter operates over a wide range of switching frequencies (10-25MHz) and achieves better than 94% peak efficiency while consuming a quiescent current of only 2μA/MHz.
{"title":"A 10–25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW","authors":"Q. Khan, S. Kim, Mrunmay Talegaonkar, A. Elshazly, A. Rao, Nathanael Griesert, Greg Winter, W. McIntyre, P. Hanumolu","doi":"10.1109/VLSIC.2014.6858439","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858439","url":null,"abstract":"A time-based PID compensator that combines the advantages of both analog and digital controllers is used to implement a high frequency low quiescent current buck converter. Fabricated in 180nm CMOS process, the proposed buck converter operates over a wide range of switching frequencies (10-25MHz) and achieves better than 94% peak efficiency while consuming a quiescent current of only 2μA/MHz.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123629979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858391
Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, A. Elshazly, P. Hanumolu
A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented. Fabricated in 65nm CMOS process, the prototype PLL consumes 3.7mW at 4.5GHz output frequency and achieves better than -106dBc/Hz in-band noise and 490fsrms integrated jitter. This translates to a FoMJ of -240.5dB, which is the best among the reported fractional-N PLLs.
{"title":"A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with −106dBc/Hz In-band noise using time amplifier based TDC","authors":"Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, A. Elshazly, P. Hanumolu","doi":"10.1109/VLSIC.2014.6858391","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858391","url":null,"abstract":"A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented. Fabricated in 65nm CMOS process, the prototype PLL consumes 3.7mW at 4.5GHz output frequency and achieves better than -106dBc/Hz in-band noise and 490fsrms integrated jitter. This translates to a FoMJ of -240.5dB, which is the best among the reported fractional-N PLLs.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"223 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121477854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858452
Chin-Yu Lin, Tai-Cheng Lee
A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1st and the 2nd stages and active residue amplification between the 2nd and the 3rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a 5-MHz input and 60.1 dB near Nyquist-rate.
{"title":"A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique","authors":"Chin-Yu Lin, Tai-Cheng Lee","doi":"10.1109/VLSIC.2014.6858452","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858452","url":null,"abstract":"A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1st and the 2nd stages and active residue amplification between the 2nd and the 3rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a 5-MHz input and 60.1 dB near Nyquist-rate.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124433019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858441
Wei-Chung Chen, Yung-Sheng Huang, M. Chien, Ying-Wei Chou, Hsin-Chieh Chen, Yi-Ping Su, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee
For high efficiency, the proposed constant on-time controlled switching regulator (SWR) directly supplies to Wi-Fi systems without cascading any low dropout regulators. On-time value adjusted by the proposed transient-enhanced technique greatly reduces transient voltage variations. Besides, an asynchronous auto-zero technique is used to minimize offset voltage effect to ±0.5% in steady state. Experimental results show voltage variation is smaller than ±3% and peak efficiency is 95% with a small silicon area of 0.0019 mm2, which is only one-twentieth of conventional design. The proposed well-regulated SWR can improve error vector magnitude (EVM) from -27.2 dB to -33.6 dB.
{"title":"±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems","authors":"Wei-Chung Chen, Yung-Sheng Huang, M. Chien, Ying-Wei Chou, Hsin-Chieh Chen, Yi-Ping Su, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee","doi":"10.1109/VLSIC.2014.6858441","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858441","url":null,"abstract":"For high efficiency, the proposed constant on-time controlled switching regulator (SWR) directly supplies to Wi-Fi systems without cascading any low dropout regulators. On-time value adjusted by the proposed transient-enhanced technique greatly reduces transient voltage variations. Besides, an asynchronous auto-zero technique is used to minimize offset voltage effect to ±0.5% in steady state. Experimental results show voltage variation is smaller than ±3% and peak efficiency is 95% with a small silicon area of 0.0019 mm2, which is only one-twentieth of conventional design. The proposed well-regulated SWR can improve error vector magnitude (EVM) from -27.2 dB to -33.6 dB.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125805955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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