Transaction-based debugging of system-on-chips with patterns

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI:10.1109/ICCD.2009.5413157

A. M. Gharehbaghi, M. Fujita

引用次数: 28

Abstract

This paper presents a debug method for system communications in post-silicon verification. First, we extract transaction sequences at run-time using on-chip circuits and store them in a trace buffer. Then, we read the stored transactions and analyze them with software. The analysis software tries to find certain patterns in the extracted transactions that are defined by our transaction debug pattern specification language (TDPSL). We have also defined a number of standard patterns for common communication problems such as race and deadlock in TDPSL. To show the feasibility of the method, it is applied to a number of on chip buses. It is shown that the area overhead of the method is very low. Also we have implemented the analysis software and shown that it is memory efficient, scalable and effective to find bugs. The proposed method can also be applied to fault analysis including transient faults.

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带模式的片上系统的基于事务的调试

本文提出了一种后硅验证系统通信的调试方法。首先，我们在运行时使用片上电路提取事务序列，并将它们存储在跟踪缓冲区中。然后，我们读取存储的事务并使用软件进行分析。分析软件试图在提取的事务中找到由我们的事务调试模式规范语言(TDPSL)定义的某些模式。我们还为TDPSL中的竞争和死锁等常见通信问题定义了许多标准模式。为了证明该方法的可行性，将其应用于多个片上总线。结果表明，该方法的面积开销非常低。此外，我们已经实现了分析软件，并表明它是内存高效，可扩展和有效的发现漏洞。该方法也可用于包括暂态故障在内的故障分析。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2009 IEEE International Conference on Computer Design

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