{"title":"Scalable power delivery design methodology for SoC on cost driven platforms","authors":"K. Cai, S. Ji","doi":"10.1109/SAPIW.2015.7237389","DOIUrl":null,"url":null,"abstract":"A scalable power delivery analysis methodology is described for SoCs targeted at cost-driven platforms. The methodology is applied at different design stages to consolidate a hundred independent power supplies at bump level to half that at solder ball level and to five major power supplies at board level.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAPIW.2015.7237389","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A scalable power delivery analysis methodology is described for SoCs targeted at cost-driven platforms. The methodology is applied at different design stages to consolidate a hundred independent power supplies at bump level to half that at solder ball level and to five major power supplies at board level.
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