Chih-Hsien Lin, Yi-Hsien Lin, Chih-Feng Wu, M. Shiue, Chorng-Kuang Wang
{"title":"Cost efficient FEQ implementation for IEEE 802.16a OFDM transceiver","authors":"Chih-Hsien Lin, Yi-Hsien Lin, Chih-Feng Wu, M. Shiue, Chorng-Kuang Wang","doi":"10.1109/VDAT.2009.5158118","DOIUrl":null,"url":null,"abstract":"Based on SR transformation, a cost efficient FEQ is proposed for OFDM transceiver of IEEE 802.16a WMAN without SNR loss over the multipath fading channel. The cost efficient FEQ is composed of three parts: channel estimation, filtering and updating processes. Significantly, the computing complexity of multiplication for the cost efficient approach can totally yield 19% reduction compared with the conventional approach. In view of the memory arrangement in VLSI design, the area and power can be decreased by 70% and 50% respectively for the channel estimation. In the updating, 18% reduction is obtained for both area and power. According to the uncoded SER simulation, the proposed approach is identical with the conventional approach. Finally, the cost efficient FEQ is demonstrated by FPGA board.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Based on SR transformation, a cost efficient FEQ is proposed for OFDM transceiver of IEEE 802.16a WMAN without SNR loss over the multipath fading channel. The cost efficient FEQ is composed of three parts: channel estimation, filtering and updating processes. Significantly, the computing complexity of multiplication for the cost efficient approach can totally yield 19% reduction compared with the conventional approach. In view of the memory arrangement in VLSI design, the area and power can be decreased by 70% and 50% respectively for the channel estimation. In the updating, 18% reduction is obtained for both area and power. According to the uncoded SER simulation, the proposed approach is identical with the conventional approach. Finally, the cost efficient FEQ is demonstrated by FPGA board.